1. Field of the Invention
This invention relates generally to a data processing system in a communications environment and more specifically to the use of a random access memory to store responses to asynchronously generated information bus transfer cycles.
2. Description of the Prior Art
In a system having a plurality of subsystems coupled over a common bus, an orderly system must be provided by which bidirectional transfer of information may be provided between such devices. Such a system is described in U.S. Pat. No. 3,993,981 entitled "Apparatus for Processing Data Transfer Requests in a Data Processing System". Apparatus is included in each subsystem for requesting the area of the bus for the transfer of information to another one of the subsystems during an asynchronously generated bus transfer cycle. Response logic is also included in each subsystem for acknowledging the receiving of the information during the asynchronously generated transfer cycle.
Typical of the subsystems coupled to the system bus is a communication subsystem such as described in U.S. Pat. No. 4,261,033 issued Apr. 7, 1981 entitled "Communications Processor Employing Line Dedicated Memory Tables for Supervising Data Transfers". This communication subsystem is responsive to input/output commands received over the system bus from a central processing unit. Apparatus in the communication subsystem generates an acknowledge response if the communication controller receives the input/output command, and generates a negative acknowledge signal if the communication controller is not able to receive the input/output command. Since the bus transfers are asynchronous, delays in the response will reduce the overall throughput of the system.
Certain input/output commands require that communication control blocks stored in a random access memory be available to allow the execution of these commands. Apparatus in the communication subsystem generates a positive or negative acknowledge response to these input/output commands.
The apparatus requires a considerable amount of hardware and requires a number of logic steps in order to send a response out on the system bus.
The hardware required is reduced by the use of a microprocessor controlling communication lines through the use of channel control blocks stored in a memory. Such a system is described in U.S. Pat. No. 4,133,030 entitled "Control System Providing for the Transfer of Data in a Communications Processing System Employing Channel Dedicated Control Blocks". This system, however, limited the throughput by restricting the number of communication lines that could be processed.
It should be understood that the references cited herein are those which the Applicants are aware of and are presented to acquaint the reader with the level of skill in the art and may not be the closest reference to the invention. No representation is made that any search has been conducted by the Applicants.